Semiconductor device

ABSTRACT

A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first circuit includes a third circuit storing at least one pair of first data including a history of a branch instruction and a first address corresponding to the branch instruction; a fourth circuit comparing a second address of an instruction and the first address; and a fifth circuit selecting the first data of one pair among the at least one pair in accordance with a comparison result. The second circuit includes a plurality of sixth circuits having a function of generating a signal for testing operation of the first circuit in accordance with second data, and a function of storing the at least one pair together with the second circuit after the operation is tested.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/542,859, filed Nov. 17, 2014, now allowed, which claims the benefitof a foreign priority application filed in Japan as Serial No.2013-241608 on Nov. 22, 2013, both of which are incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an object, a method, or a manufacturingmethod. In addition, the present invention relates to a process, amachine, manufacture, or a composition of matter. In particular, oneembodiment of the present invention relates to a semiconductor device, adisplay device, a light-emitting device, a power storage device, amemory device, a driving method thereof, or a manufacturing methodthereof. For example, the present invention relates to a semiconductordevice including a test circuit.

2. Description of the Related Art

A built-in self-test (BIST) is a test technique for providing a functionof a tester, which is semiconductor test equipment, in an integratedcircuit. It is known that the use of the BIST cuts the costs requiredfor an operation test of a semiconductor device and increases the speedof the operation test. Patent Document 1 discloses a technique forachieving a self-test (BIST) circuit by using a field-programmable gatearray (FPGA).

REFERENCE

Patent Document 1: Japanese Published Patent Application No. H5-142297

SUMMARY OF THE INVENTION

To improve the quality of an operation test with the BIST or to performan operation test on a semiconductor device with complicated functions,a wide variety of test patterns are required to be prepared. As thenumber and kind of test patterns to be generated increase, the size of acircuit having a function of generating test patterns (hereinafterreferred to as BIST circuit) increases, and the area overhead of asemiconductor device including the BIST circuit and a circuit to betested is likely to increase.

Since test patterns to be generated in the BIST circuit are set in thedesign phase, a new test pattern is required to be supplied from theoutside of the semiconductor device to perform an additional operationtest. In this case, advantages of the BIST, such as a higher-speedoperation test and lower cost for the operation test, are not obtained.

Branch prediction is a method in which whether a branch condition of abranch instruction is satisfied or not is predicted in advance, andbased on the prediction, an instruction predicted to be executed next isexecuted speculatively before satisfaction of the branch condition isdetermined. When the accuracy of branch prediction can be increased, abranch hazard in pipelining can be prevented, resulting in higherperformance of a processor.

In view of the foregoing technical background, an object of oneembodiment of the present invention is to provide a semiconductor devicein which the area of a circuit that is unnecessary during normaloperation is small. Another object of one embodiment of the presentinvention is to provide a semiconductor device capable of generating anew test pattern after the design phase. Another object of oneembodiment of the present invention is to provide a semiconductor devicewith high accuracy of branch prediction.

An object of one embodiment of the present invention is to provide anovel semiconductor device or the like. Note that the description ofthese objects does not disturb the existence of other objects. In oneembodiment of the present invention, there is no need to achieve all theobjects. Other objects will be apparent from and can be derived from thedescription of the specification, the drawings, the claims, and thelike.

A semiconductor device of one embodiment of the present inventionincludes a first circuit and a second circuit. The first circuitincludes a third circuit storing at least one pair of first dataincluding a history of whether a branch condition of a branchinstruction is satisfied or not, and a first address corresponding tothe branch instruction; a fourth circuit comparing a second address ofan instruction and the first address; and a fifth circuit selecting thefirst data of one pair among the at least one pair in accordance with acomparison result. The second circuit includes a plurality of sixthcircuits with a function of generating a signal for testing operation ofthe first circuit when electrical continuity between the sixth circuitsand a logical value of an output signal with respect to that of an inputsignal are controlled in accordance with second data, and a function ofstoring the at least one pair together with the second circuit after theoperation is tested in accordance with the signal.

A semiconductor device of one embodiment of the present inventionincludes a first circuit and a second circuit. The first circuitincludes a third circuit storing at least one pair of first dataincluding a history of whether a branch condition of a branchinstruction is satisfied or not, and a first address corresponding tothe branch instruction; a fourth circuit comparing a second address ofan instruction and the first address; and a fifth circuit selecting thefirst data of one pair among the at least one pair in accordance with acomparison result. The second circuit includes a sixth circuit storingsecond data; and a plurality of seventh circuits generating a signal fortesting operation of the first circuit when electrical continuitybetween the seventh circuits is controlled by the sixth circuit inaccordance with the second data. The sixth circuit has a function ofstoring the at least one pair together with the second circuit after theoperation is tested in accordance with the signal.

In the semiconductor device of one embodiment of the present invention,the sixth circuit may include a plurality of pairs each including afirst transistor and a second transistor that is turned on and off inaccordance with the second data input through the first transistor.

In the semiconductor device of one embodiment of the present invention,the first transistor may include an oxide semiconductor film including achannel formation region.

In the semiconductor device of one embodiment of the present invention,the oxide semiconductor film may contain In, Ga, and Zn.

One embodiment of the present invention can provide a semiconductordevice in which the area of a circuit that is unnecessary during normaloperation is small. Another embodiment of the present invention canprovide a semiconductor device capable of generating a new test patternafter the design phase. Another embodiment of the present invention canprovide a semiconductor device with high accuracy of branch prediction.

One embodiment of the present invention can provide a novelsemiconductor device or the like. Note that the description of theseeffects does not disturb the existence of other effects. One embodimentof the present invention does not necessarily achieve all the aboveeffects. Other effects will be apparent from and can be derived from thedescription of the specification, the drawings, the claims, and thelike.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings,

FIG. 1 illustrates a structure of a semiconductor device;

FIG. 2 illustrates a structure of a semiconductor device;

FIG. 3 illustrates a structure of a semiconductor device;

FIGS. 4A to 4C each illustrate a specific structural example of acircuit 17;

FIG. 5 illustrates a structure of a logic array;

FIG. 6 illustrates a structure of a switch circuit;

FIG. 7 illustrates a structure of a semiconductor device;

FIG. 8 illustrates a structure of a circuit 33;

FIG. 9 illustrates a structural example of an integrated circuit;

FIGS. 10A to 10C illustrate a structure of a switch circuit;

FIG. 11 illustrates a structure of a switch circuit;

FIGS. 12A to 12C illustrate a structure of a transistor;

FIGS. 13A to 13C illustrate a structure of a transistor;

FIG. 14 illustrates a cross-sectional structure of a semiconductordevice; and

FIGS. 15A to 15F illustrate electronic devices.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below in detailwith reference to the drawings. Note that the present invention is notlimited to the following description, and it is easily understood bythose skilled in the art that the mode and details can be variouslychanged without departing from the spirit and scope of the presentinvention. Therefore, the present invention should not be construed asbeing limited to the description of the embodiments below.

Note that the present invention includes, in its category, anysemiconductor device including semiconductor integrated circuit, such asRF tags and semiconductor display devices. A semiconductor displaydevice includes, in its category, semiconductor display devices in whicha semiconductor integrated circuit is included in a driver circuit, suchas liquid crystal display devices, light-emitting devices in which alight-emitting element typified by an organic light-emitting element isprovided in each pixel, electronic paper, digital micromirror devices(DMD), plasma display panels (PDP), and field emission displays (FED).

Note that the term “connection” in this specification refers toelectrical connection and corresponds to a configuration in whichcurrent, voltage, or potential can be supplied or transmitted.Therefore, a configuration in which two circuits or two elements areconnected does not necessarily refer to a configuration in which theyare directly connected, and also refers to a configuration in which theyare indirectly connected through an element such as a wiring, aresistor, a diode, or transistor so that current, voltage, or potentialcan be supplied or transmitted. In addition, even when differentcomponents are connected to each other in a circuit diagram, there isactually a case where one conductive film has functions of a pluralityof components, such as a case where part of a wiring serves as anelectrode. The term “connection” in this specification also means such acase where one conductive film has functions of a plurality ofcomponents.

A source of a transistor means a source region that is part of asemiconductor film functioning as an active layer or a source electrodeelectrically connected to the semiconductor film. Similarly, a drain ofa transistor means a drain region that is part of a semiconductor filmfunctioning as an active layer or a drain electrode electricallyconnected to the semiconductor film. A gate means a gate electrode.

The terms “source” and “drain” of a transistor interchange with eachother depending on the type of the channel of the transistor or thelevels of potentials applied to the terminals. In general, in ann-channel transistor, a terminal to which a lower potential is appliedis called a source, and a terminal to which a higher potential isapplied is called a drain. Furthermore, in a p-channel transistor, aterminal to which a lower potential is applied is called a drain, and aterminal to which a higher potential is applied is called a source. Inthis specification, the connection relation of the transistor isdescribed assuming that the source and the drain are fixed in some casesfor convenience; actually, the names of the source and the draininterchange with each other depending on the relation of the potentials.

Structural Example 1 of Semiconductor Device

FIG. 1 illustrates a structural example of a semiconductor device 10 ofone embodiment of the present invention. The semiconductor device 10illustrated in FIG. 1 includes an integrated circuit 11 and anintegrated circuit 12. The integrated circuit 11 includes a variety oflogic circuits such as a sequential circuit and a combinational circuit.Each of the integrated circuits 11 and 12 includes at least twotransistors, and they can be referred to as a first circuit, a secondcircuit, and the like or simply circuits.

The integrated circuit 11 includes a memory circuit 13, a comparatorcircuit 14, and a selector circuit 15. The memory circuit 13 includes aregion for storing at least one pair of first data and a first address.The first data includes a history or a prediction of whether a branchcondition of a branch instruction is satisfied, and the first addresscorresponds to the branch instruction. Specifically, FIG. 1 illustratesthat the memory circuit 13 includes a first memory region 13 a and asecond memory region 13 b, the first address is stored in the firstmemory region 13 a, and the first data is stored in the second memoryregion 13 b. In FIG. 1, the memory circuit 13 stores n−1 pairs BR of thefirst data and the first address, represented as the pairs BR1 to BRn−1(n−1 is an integer).

As the memory circuit 13, a flip-flop, a register, or an SRAM can beused, for example. When the data capacity of the second memory region 13b for storing one pair BR is 2 bits, for example, the state is changeddepending on whether a branch condition is satisfied or not between afirst state where branch is least likely to be executed (strongly nottaken (“00”)), a second state where branch is less likely to be executed(weakly not taken (“01”)), a third state where branch is more likely tobe executed (weakly taken (“10”)), and a fourth state where branch ismost likely to be executed (strongly taken (“11”)). Thus, the secondmemory region 13 b can store a history of whether the branch conditionof a branch instruction is satisfied or not.

Specifically, when the branch condition is satisfied, the state istransferred toward strongly taken. On the other hand, when the branchcondition is not satisfied, the state is transferred toward strongly nottaken. It can be predicted that a branch instruction by which branchconditions have been satisfied successively has a higher probability ofsatisfying a branch condition next; consequently, the above structurecan increase the probability of predicting whether a branch condition ofthe branch instruction is satisfied or not.

Then, when the history corresponding to the branch instruction is thefirst state (strongly not taken (“00”)) or the second state (weakly nottaken (“01”)), it can be predicted that the branch condition will not besatisfied. In contrast, when the history corresponding to the branchinstruction is the third state (weakly taken (“10”)) or the fourth state(strongly taken (“11”)), it can be predicted that the branch conditionwill be satisfied. When the branch condition is predicted to besatisfied, the semiconductor device 10 performs speculative execution.

Note that the data capacity of the second memory region 13 b for storingone pair BR may be 1 bit or 3 bits or more.

Memory circuits such as the memory circuit 13 may have another functionas well as a function of storing data, for example, and are thusreferred to as a first circuit, a second circuit, and the like or simplycircuits in some cases.

The comparator circuit 14 has a function of comparing the first addressand a second address (current PC) corresponding to an address of aninstruction to be executed next. Specifically, FIG. 1 illustrates thatthe integrated circuit 11 includes n−1 comparator circuits 14(comparator circuits 14-1 to 14-(n−1)). The comparator circuits 14-1 to14-(n−1) correspond to the n−1 pairs BR stored in the memory circuit 13.The n−1 comparator circuits 14 have a function of comparing the secondaddress and the corresponding n−1 first addresses included in the n−1pairs BR.

Comparator circuits such as the comparator circuit 14 may have anotherfunction in addition to a function of comparing addresses and data, forexample, and are thus referred to as a first circuit, a second circuit,and the like or simply circuits in some cases.

The selector circuit 15 has a function of selecting the first dataincluded in one pair BR among the n−1 pairs BR in accordance with theresults of the comparison in the comparator circuits 14. As the selectorcircuit 15, a multiplexer or the like can be used. For example, when thefirst address and the second address that are compared in the comparatorcircuit 14-i (i is a natural number of n−1 or less) among the n−1comparator circuits 14 are matched, the selector circuit 15 selects thefirst data included in the pair BRi.

Selector circuits such as the selector circuit 15 may have anotherfunction in addition to a function of selecting data, for example, andare thus referred to as a first circuit, a second circuit, and the likeor simply circuits in some cases.

Note that a signal including the results of comparison in the comparatorcircuits 14 as information can also be generated by a circuit differentfrom the selector circuit 15, for example, an OR circuit.

When the comparison results show no match between all the firstaddresses and the second address, the selector circuit 15 outputs asignal including information about address mismatch.

The integrated circuit 12 includes a logic array 16 and a memory circuit19. The logic array 16 includes a plurality of circuits 17. Each of thecircuits 17 includes a memory circuit 18 with a function of maintainingan input signal. As the memory circuit 18, a sequential circuit such asa flip-flop or a counter can be used, for example.

The memory circuit 19 has a function of storing second data includinginformation on a circuit composed of the circuits 17. Specifically, thesecond data includes, as circuit information, electrical continuitybetween the circuits 17 and the logical value of an output signal withrespect to that of an input signal in each circuit 17. Furthermore, thememory circuit 19 may have a function of controlling electricalcontinuity between the circuits 17 in accordance with the second data.

The circuits 17 are provided with a function of generating a signal fortesting the operating state of the integrated circuit 11 (hereinafterreferred to as test pattern) by controlling electrical continuitybetween the circuits 17 and the logical value of an output signal withrespect to that of an input signal in each circuit 17 in accordance withthe second data stored in the memory circuit 19.

The integrated circuit 11 operates in accordance with a test patterngenerated in the integrated circuit 12 and outputs a signal accordingly.In the semiconductor device 10 of one embodiment of the presentinvention, a function of evaluating the operating state of theintegrated circuit 11 by using the output signal may be added to thecircuits 17 depending on the second data stored in the memory circuit19.

In one embodiment of the present invention, electrical continuitybetween the circuits 17 and the logical value of an output signal withrespect to that of an input signal in each circuit 17 are controlled inthe integrated circuit 12, whereby kinds of test patterns generated inthe circuits 17 can be changed. The circuits 17 can function ascombinational circuits and sequential circuits, resulting in a widevariety of combinations of the logical values of output signals withrespect to those of input signals in the circuits 17. Thus, in thesemiconductor device 10 of one embodiment of the present invention,kinds of test patterns generated in the circuits 17 can be increasedwith a smaller number of gates of the circuits 17. Moreover, anadditional test for the operating state of the integrated circuit 11 canbe performed without supply of a new test pattern from the outside ofthe semiconductor device 10.

A test pattern generated in the circuits 17 may be a signal for testingthe operating state of some of the circuits included in the integratedcircuit 11 or a signal for testing the operating state of the entireintegrated circuit 11. For example, when the integrated circuit 11includes a memory circuit different from the memory circuit 13, thecircuits 17 can generate a test pattern for testing the operating stateof the memory circuit. When the integrated circuit 11 includes an analogcircuit such as a phase locked loop, the circuits 17 can generate a testpattern for testing the operating state of the analog circuit.

In one embodiment of the present invention, when a test for theoperating state of the integrated circuit 11 is not performed, that is,when the semiconductor device 10 is in normal operation, the integratedcircuit 12 has a function of storing at least one pair BR of the firstdata and the first address in the memory circuit 18 or the memorycircuit 19. FIG. 2 schematically illustrates an operating state of thesemiconductor device 10 in which the memory circuit 18 has a function ofstoring at least one pair BR of the first data and the first addressduring normal operation.

FIG. 2 illustrates an example where a function of storing a pair BRn ofthe first data and the first address is added to the memory circuit 18by controlling electrical continuity between the circuits 17 in FIG. 1and the logical value of an output signal with respect to that of aninput signal in each circuit 17 in the logic array 16. In FIG. 2, thememory circuit 18 with a function of storing the pair BRn among theplurality of memory circuits 18 is shown as a memory circuit 18 a.

Moreover, FIG. 2 illustrates the case where a function of the comparatorcircuit 14-n is added to any of the circuits 17 by controllingelectrical continuity between the circuits 17 and the logical value ofan output signal with respect to that of an input signal in each circuit17 in the logic array 16. Specifically, the comparator circuit 14-n hasa function of comparing the second address and the first addressincluded in the pair BRn.

In the semiconductor device 10 in FIG. 2, the selector circuit 15 has afunction of selecting the first data included in one pair BR among the npairs BR in accordance with the results of the comparison in thecomparator circuits 14-1 to 14-n. For example, when the first addressand the second address that are compared in the comparator circuit 14-j(j is a natural number of n or less) among the comparator circuits 14-1to 14-n are matched, the selector circuit 15 selects the first dataincluded in the pair BRj. When the comparison results in all thecomparator circuits 14-1 to 14-n show no match between the firstaddresses and the second address, the selector circuit 15 outputs asignal including information about address mismatch.

When a test for the operating state of the integrated circuit 11 isperformed as illustrated in FIG. 1, data “0” indicating that the firstaddress in the pair BRn stored in the memory circuit 18 a in FIG. 2 doesnot match the second address is transmitted from the integrated circuit12 to the selector circuit 15 through a signal line 90. At this time, ifthe first address in the pair BRn stored in the memory circuit 18 a inFIG. 2 is transmitted from the integrated circuit 12 to the selectorcircuit 15 through a signal line 91, the first data in the pair BRn isnot selected in the selector circuit 15.

Alternatively, in order not to select the first data in the pair BRn bythe selector circuit 15 during a test for the operating state of theintegrated circuit 11, identification information showing that all datastored in the memory circuits 18 are invalid may be input from theintegrated circuit 12 to the integrated circuit 11.

FIG. 2 illustrates the example where a function of storing one pair BRnis added to one of the memory circuits 18 and a function of onecomparator circuit 14-n is added to one of the circuits 17.Alternatively, in the semiconductor device 10 of one embodiment of thepresent invention, it is possible that a function of storing a pluralityof pairs BR is added to the memory circuits 18 and a function of aplurality of comparator circuits 14 corresponding to the pairs BR isadded to one of the circuits 17.

FIG. 2 illustrates the example where a function of the comparatorcircuit 14-n is added to one of the circuits 17 in such a manner thatthe logic array 16 controls electrical continuity between the circuits17 and the logical value of an output signal with respect to that of aninput signal in each circuit 17. Alternatively, in the semiconductordevice 10 of one embodiment of the present invention, the integratedcircuit 12 may include the comparator circuit 14-n in addition to thelogic array 16.

A first state where the integrated circuit 12 can generate a testpattern and a second state where the integrated circuit 12 has afunction of storing the pair BR can be switched in accordance with aninstruction input from an input device (not shown). Alternatively, it ispossible that an instruction to switch between these states is stored ina memory device (not shown) included in the integrated circuit 11 andthe state is switched in accordance with the instruction when thesemiconductor device 10 is powered on.

Switching of a signal path due to the state switching may be performedby a switch (not shown).

In one embodiment of the present invention, the pair BR of the firstdata and the first address is stored in the memory circuit 18 as well asin the memory circuit 13, whereby the semiconductor device 10 can storea larger number of pairs of the first data including a history ofwhether a branch condition of a branch instruction is satisfied or notand the first address corresponding to the branch instruction. With thisstructure, the probability of predicting whether a branch condition of abranch instruction is satisfied or not can be increased even when morecomplicated pipelining is required; thus, the performance of thesemiconductor device can be increased. Accordingly, in the semiconductordevice 10 of one embodiment of the present invention, the memory circuit18 is used not only in a test for the operating state of the integratedcircuit 11 but also in normal operation to drive the semiconductordevice 10. Thus, the area of a circuit that is unnecessary during normaloperation can be reduced in the semiconductor device 10 of oneembodiment of the present invention.

Structural Example 2 of Semiconductor Device

FIG. 3 schematically illustrates an operating state of the semiconductordevice 10 in which the memory circuit 19 has a function of storing atleast one pair BR of the first data and the first address during normaloperation.

Specifically, FIG. 3 illustrates an example where a function of storingthe pair BRn of the first data and the first address is added to thememory circuit 19 and the integrated circuit 12 includes the comparatorcircuit 14-n. The comparator circuit 14-n has a function of comparingthe first address included in the pair BRn and the second addresscorresponding to an instruction to be executed next.

In the semiconductor device 10 in FIG. 3, the selector circuit 15 has afunction of selecting the first data included in one pair BR among the npairs BR in accordance with the results of comparison in the comparatorcircuits 14-1 to 14-n. For example, when the first address and thesecond address that are compared in the comparator circuit 14-j amongthe comparator circuits 14-1 to 14-n are matched, the selector circuit15 selects the first data included in the pair BRj. When the comparisonresults in all the comparator circuits 14-1 to 14-n show no matchbetween the first addresses and the second address, the selector circuit15 outputs a signal including information about address mismatch.

When a test for the operating state of the integrated circuit 11 isperformed as illustrated in FIG. 1, data “0” indicating that the firstaddress in the pair BRn stored in the memory circuit 19 in FIG. 3 doesnot match the second address is transmitted from the integrated circuit12 to the selector circuit 15 through the signal line 90. At this time,if the first address in the pair BRn stored in the memory circuit 19 inFIG. 3 is transmitted from the integrated circuit 12 to the selectorcircuit 15 through the signal line 91, the first data in the pair BRn isnot selected in the selector circuit 15.

Alternatively, in order not to select the first data in the pair BRn bythe selector circuit 15 during a test for the operating state of theintegrated circuit 11, identification information showing that all datastored in the memory circuit 19 is invalid may be input from theintegrated circuit 12 to the integrated circuit 11.

FIG. 3 illustrates the example where a function of storing one pair BRnis added to the memory circuit 19 and the integrated circuit 12 includesone comparator circuit 14-n. Alternatively, in the semiconductor device10 of one embodiment of the present invention, it is possible that afunction of storing a plurality of pairs BR is added to the memorycircuit 19 and the integrated circuit 12 includes a plurality ofcomparator circuits 14 corresponding to the pairs BR.

The first state where the integrated circuit 12 can generate a testpattern and the second state where the integrated circuit 12 has afunction of storing the pair BR can be switched in accordance with aninstruction input from an input device (not shown). Alternatively, it ispossible that an instruction to switch between these states is stored ina memory device (not shown) included in the integrated circuit 11 andthe state is switched in accordance with the instruction when thesemiconductor device 10 is powered on.

Switching of a signal path due to the state switching may be performedby a switch (not shown).

In one embodiment of the present invention, the pair BR of the firstdata and the first address is stored in the memory circuit 19 as well asin the memory circuit 13, whereby the semiconductor device 10 can storea larger number of pairs of the first data including a history ofwhether a branch condition of a branch instruction is satisfied or notand the first address corresponding to the branch instruction. With thisstructure, the probability of predicting whether a branch condition of abranch instruction is satisfied or not can be increased even when morecomplicated pipelining is required; thus, the performance of thesemiconductor device can be increased. Accordingly, in the semiconductordevice 10 of one embodiment of the present invention, the memory circuit19 is used not only in a test for the operating state of the integratedcircuit 11 but also in normal operation to drive the semiconductordevice 10. Thus, the area of a circuit that is unnecessary during normaloperation can be reduced in the semiconductor device 10 of oneembodiment of the present invention.

Structural Examples of Circuit 17

Next, structural examples of the circuit 17 included in the integratedcircuit 12 will be described.

FIG. 4A illustrates one embodiment of the circuit 17. The circuit 17 inFIG. 4A includes a lookup table (LUT) 20 and the memory circuit 18. TheLUT 20 includes a memory circuit 21 having a function of temporarilystoring the second data transmitted from the memory circuit 19. Thelogical value of an output signal of the LUT 20 with respect to that ofan input signal input to an input terminal 22 is determined inaccordance with the second data. The memory circuit 18 holds dataincluded in the output signal of the LUT 20 and outputs an output signalcorresponding to the data from an output terminal 23 in synchronizationwith a signal CLK.

Note that it is possible that the circuit 17 includes a multiplexerbetween the LUT 20 and the memory circuit 18 and whether the outputsignal from the LUT 20 passes through the memory circuit 18 or not isselected by the multiplexer.

The type of the memory circuit 18 may be defined by data includingcircuit information. Specifically, the memory circuit 18 may function asany of a D flip-flop, a T flip-flop, a JK flip-flop, and an RS flip-flopin accordance with data including circuit information.

FIG. 4B illustrates another embodiment of the circuit 17. The circuit 17illustrated in FIG. 4B includes an AND circuit 24 in addition to thecomponents of the circuit 17 illustrated in FIG. 4A. To the AND circuit24, a signal from the memory circuit 18 is supplied as a positive logicinput, and a potential of a signal INIT is supplied as a negative logicinput. Thus, the potential of the output terminal 23 can be initializedin accordance with the potential of the signal INIT.

FIG. 4C illustrates another embodiment of the circuit 17. The circuit 17illustrated in FIG. 4C includes a multiplexer 25 in addition to thecomponents of the circuit 17 illustrated in FIG. 4A. The circuit in FIG.4C also includes a memory circuit 26 that has a function of storing datafor determining the logical value of an output signal with respect tothat of an input signal of the multiplexer 25.

The logical value of an output signal with respect to that of an inputsignal of the LUT 20 is determined in accordance with the second dataincluded in the memory circuit 21. An output signal from the LUT 20 andan output signal from the memory circuit 18 are input to the multiplexer25. The multiplexer 25 has a function of selecting and outputting one ofthe two output signals in accordance with data stored in the memorycircuit 26. An output signal from the multiplexer 25 is output from theoutput terminal 23.

Structural Example of Logic Array

FIG. 5 illustrates a structural example of the logic array 16. The logicarray 16 includes a plurality of circuits 17, a plurality of wirings 30electrically connected to input terminals or output terminals of thecircuits 17, and switch circuits 31 with a function of controllingelectrical continuity between the wirings 30. Electrical continuitybetween the circuits 17 is controlled by the wirings 30 and the switchcircuits 31. Electrical continuity between the wirings 30, which iscontrolled by the switch circuits 31, is determined based on the seconddata stored in the memory circuit 19 illustrated in FIG. 1.

The logic array 16 illustrated in FIG. 5 may be provided with a wiringhaving a function of supplying the signal CLK or a signal RES to thecircuits 17, in addition to the wirings 30 electrically connected to theinput terminals or output terminals of the circuits 17. The signal CLKcan be used to control timing of signal output from the memory circuit18 in any of the circuits 17 illustrated in FIGS. 4A to 4C, for example.Moreover, the memory circuit 18 in any of the circuits 17 illustrated inFIGS. 4A to 4C may have a function of initializing stored data inaccordance with the signal RES, for example.

FIG. 6 illustrates a structural example of the switch circuit 31 thatcontrols electrical continuity between wirings 30 a to 30 d included inthe wirings 30. Specifically, the switch circuit 31 in FIG. 6 includesswitches 32 a to 32 f. Transistors can be used as the switches 32 a to32 f.

Note that one transistor can be used as one of the switches 32 a to 32f, or two or more transistors can be used as one of the switches 32 a to32 f. When a plurality of transistors are used as one of the switches 32a to 32 f, the transistors may be connected to each other in parallel,series, or series-parallel.

Note that in this specification, a state in which transistors areconnected to each other in series means, for example, a state in whichonly one of a source and a drain of a first transistor is connected toonly one of a source and a drain of a second transistor. In addition, astate in which transistors are connected to each other in parallel meansa state in which one of a source and a drain of a first transistor isconnected to one of a source and a drain of a second transistor and theother of the source and the drain of the first transistor is connectedto the other of the source and the drain of the second transistor.

The on/off state (switching) of the switches 32 a to 32 f is determinedby the second data stored in the memory circuit 19 illustrated in FIG.1.

Specifically, the switch 32 a has a function of controlling electricalcontinuity between the wiring 30 a and the wiring 30 c. The switch 32 bhas a function of controlling electrical continuity between the wiring30 b and the wiring 30 c. The switch 32 c has a function of controllingelectrical continuity between the wiring 30 a and the wiring 30 d. Theswitch 32 d has a function of controlling electrical continuity betweenthe wiring 30 b and the wiring 30 d. The switch 32 e has a function ofcontrolling electrical continuity between the wiring 30 a and the wiring30 b. The switch 32 f has a function of controlling electricalcontinuity between the wiring 30 c and the wiring 30 d.

With the above structure, the switch circuit 31 in FIG. 6 can controlelectrical continuity between the wirings 30. Note that the switchcircuit 31 may have a function of controlling electrical continuitybetween the wirings 30 and an output terminal (not shown) of the logicarray 16.

Switch circuits such as the switch circuit 31 may have another functionin addition to a function of controlling electrical continuity betweencircuits, elements, and terminals, for example, and thus may be referredto as a first circuit, a second circuit, and the like or simplycircuits.

The integrated circuit 12 may include an I/O element, a phase lockedloop (PLL), a RAM, and a multiplier in addition to the logic array 16and the memory circuit 19 illustrated in FIG. 1. The I/O elementfunctions as an interface that controls input/output of a signal from/toan external circuit of the integrated circuit 12. The PLL has a functionof generating the signal CLK. The RAM has a function of storing dataused for logical operation. The multiplier corresponds to a logiccircuit for multiplication. The multiplier is not necessarily providedwhen the logic array 16 has a function of executing multiplication.

Specific Structural Example of Semiconductor Device

FIG. 7 is a block diagram illustrating a more specific example of thestructure of the semiconductor device 10 illustrated in FIG. 1. Althoughthe block diagram attached to this specification shows componentsclassified by their functions in independent blocks, it is difficult toclassify actual components according to their functions completely, andone component can have a plurality of functions.

Like the semiconductor device 10 illustrated in FIG. 1, thesemiconductor device 10 illustrated in FIG. 7 includes the integratedcircuit 11 and the integrated circuit 12. As in the semiconductor device10 in FIG. 1, the integrated circuit 11 in FIG. 7 includes the memorycircuit 13, at least one comparator circuit 14, and the selector circuit15. Furthermore, the semiconductor device 10 in FIG. 7 includes acircuit 33, an instruction cache 34, a main memory 35, an instructionregister 36, a data cache 37, and an execution unit 38.

The execution unit 38 has a function of generating a variety of controlsignals by decoding an instruction input from the instruction register36 and a function of performing various arithmetic operations such asfour arithmetic operations and logical operation in accordance with thecontrol signals. The data cache 37 functions as a buffer memory fortemporarily storing frequently used data, such as data read from themain memory 35, data obtained during the arithmetic operation of theexecution unit 38, or data obtained as a result of the arithmeticoperation of the execution unit 38. The instruction cache 34 functionsas a buffer memory for temporarily storing a frequently used instructionamong instructions sent to the execution unit 38 via the instructionregister 36. The circuit 33 has a function of storing an address of aninstruction to be executed next. The main memory 35 has a function ofstoring data used for the arithmetic operation in the execution unit 38and an instruction to be executed in the execution unit 38.

When the first data including a prediction of whether a branch conditionof a branch instruction is satisfied or not is input to the circuit 33,an address of an instruction to be executed next is determined in thecircuit 33 in accordance with the first data. The execution unit 38reads an instruction from an address in the instruction cache 34corresponding to the address of the instruction to be executed next,which is stored in the circuit 33, and makes the instruction register 36store the instruction. When the instruction is not stored in thecorresponding address of the instruction cache 34, the execution unit 38accesses a corresponding address of the main memory 35, reads theinstruction from the main memory 35, and makes the instruction register36 store the instruction. In this case, the instruction is also storedin the instruction cache 34.

The execution unit 38 decodes the instruction stored in the instructionregister 36 and executes processing corresponding to the instruction.When the instruction to be executed is an arithmetic instruction, anarithmetic logic unit (ALU) included in the execution unit 38 performsan arithmetic operation by using data stored in an internal register ordata stored in the data cache 37, and the result of the arithmeticoperation is stored in the internal register or the data cache 37.

Then, when instruction execution is completed, the execution unit 38accesses the circuit 33 again and repeats the above procedure ofdecoding and executing an instruction read from the instruction register36 via the instruction cache 34.

FIG. 8 illustrates an example of the structure of the circuit 33. Thecircuit 33 includes a program counter 39, an adder circuit 40, and aselector circuit 41.

The circuit 33 has a function of generating a second address (currentPC) of an instruction to be executed next in the execution unit 38. Theprogram counter 39 has a function of storing the second address (currentPC). The adder circuit 40 has a function of generating an address byadding a given increment, for example, “1” to the second address(current PC).

The selector circuit 41 has a function of selecting one of the secondaddress (current PC) output from the program counter 39, the addressgenerated in the adder circuit 40, and the first address (predictedbranch address) corresponding to a branch instruction, in accordancewith a signal SigA as a second address (next PC) of an instruction to beexecuted next in the execution unit 38.

For example, when instructions are executed in the order of address, theaddress generated in the adder circuit 40 is selected by the selectorcircuit 41 and input to the program counter 39 as the second address(current PC). When the pipeline is stopped because an instruction cannotbe executed until the arithmetic result of the previous instruction isobtained, for example, or when an instruction corresponding to anaddress generated in the adder circuit 40 cannot be carried out due to acache miss or the like, the second address (current PC) is selected bythe selector circuit 41 and input to the program counter 39 as thesecond address (current PC). When branch prediction is made that abranch condition will be satisfied, the first address (predicted branchaddress) corresponding to an address of a branch target instructionpredicted to be executed after the branch instruction is selected by theselector circuit 41 and input to the program counter 39 as the secondaddress (current PC). The first data including a history of whether abranch condition of a branch instruction is satisfied or not isreflected in the signal SigA. When branch prediction is made that abranch condition will not be satisfied, it is possible to select anaddress obtained by adding a given increment to the second address(current PC).

The second address (next PC) that is selected by the selector circuit 41and output is fetched in the program counter 39 in accordance of theedge of the signal CLK, and is output from the circuit 33 as the secondaddress (current PC).

At the time of executing a branch instruction, when the execution unit38 judges that the pair BR of the first address and the first datacorresponding to the branch instruction is not stored in the memorycircuit 13, it can add the pair BR corresponding to the branchinstruction to the memory circuit 13.

When the first address corresponding to the second address (current PC)is not stored in the memory circuit 13, the execution unit 38 generatesthe signal SigA from a signal that is output from the selector circuit15 and includes information about mismatch, and supplies the signal SigAto the circuit 33. Moreover, the first address (predicted branchaddress) becomes invalid. The signal SigA is generated so that theselector circuit 41 that receives the signal including information aboutmismatch does not select the first address (predicted branch address)corresponding to the branch instruction as the second address (next PC).

Structural Example of Integrated Circuit 12

Next, the description is made on a specific structural example of theintegrated circuit 12 in which the memory circuit 19 has a function ofcontrolling electrical continuity between the circuits 17 in accordancewith the second data including information on a circuit composed of thecircuits 17, in addition to a function of storing the second data.

FIG. 9 illustrates an example of part of the structure of the integratedcircuit 12. FIG. 9 shows a first column 43-1 including circuits 17, asecond column 43-2 including circuits 17, and a third column 43-3including circuits 17. FIG. 9 illustrates an example where the firstcolumn 43-1, the second column 43-2, and the third column 43-3 arepositioned in parallel in this order from the left.

In FIG. 9, the integrated circuit 12 includes a plurality of wirings 30shown as wirings 30-1 to 30-7.

A first output terminal of each circuit 17 in the first column 43-1 iselectrically connected to one of the wirings 30-1. A second outputterminal of each circuit 17 in the first column 43-1 is electricallyconnected to one of the wirings 30-2. A first output terminal of eachcircuit 17 in the second column 43-2 is electrically connected to one ofthe wirings 30-4. A second output terminal of each circuit 17 in thesecond column 43-2 is electrically connected to one of the wirings 30-5.A first output terminal of each circuit 17 in the third column 43-3 iselectrically connected to one of the wirings 30-3. A second outputterminal of each circuit 17 in the third column 43-3 is electricallyconnected to one of the wirings 30-7.

Note that the number of the first output terminals and the number of thesecond output terminals of each circuit 17 are not limited to one, andeither or both of the number of the first output terminals and thenumber of the second output terminals may be more than one. Note alsothat one output terminal is always connected to one wiring regardless ofthe number of the first output terminals and the number of the secondoutput terminals. Thus, when one column includes Y circuits 17 (Y is anatural number), the integrated circuit 12 at least includes Y wiringsconnected to the first output terminals and Y wirings connected to thesecond output terminals.

The first column 43-1 is placed between the wirings 30-1 and the wirings30-2. The second column 43-2 is placed between the wirings 30-4 and thewirings 30-5. The third column 43-3 is placed between the wirings 30-3and the wirings 30-7.

The wirings 30-4, which are connected to the first output terminals ofthe circuits 17 in the second column 43-2, are provided both between thefirst column 43-1 and the second column 43-2 and between the firstcolumn 43-1 and a column (not illustrated) of the circuits 17 positionedon the left side of the first column 43-1 in FIG. 9. The wirings 30-3,which are connected to the first output terminals of the circuits 17 inthe third column 43-3, are provided both between the first column 43-1and the second column 43-2 and between the second column 43-2 and thethird column 43-3. The wirings 30-6, which are connected to the firstoutput terminals of the circuits 17 (not illustrated) positioned on theright side of the third column 43-3 in FIG. 9, are provided both betweenthe second column 43-2 and the third column 43-3 and between the thirdcolumn 43-3 and a column (not illustrated) of the circuits 17 positionedon the right side of the third column 43-3.

When attention is focused on an N-th column (N is a natural number of 3or more), a plurality of wirings connected to the first output terminalsof the circuits 17 in the N-th column are provided both between the N-thcolumn and an (N−1)th column and between the (N−1)th column and an(N−2)th column. In the case where N is 2, a plurality of wiringselectrically connected to the first output terminals of the circuits 17in the second column are provided both between the second column and thefirst column and between the first column and an I/O element.

In one embodiment of the present invention, when attention is focused onthe (N−1)th column (N is a natural number of 3 or more), wirings 30electrically connected to the first output terminals of the circuits 17in the (N−1)th column, wirings 30 electrically connected to the firstoutput terminals of the circuits 17 in the N-th column, and wirings 30electrically connected to the second output terminals of the circuits 17in the (N−2)th column are electrically connected to the input terminalsof the circuits 17 in the (N−1)th column through switch circuits 31.

Specifically, in FIG. 9, for example, the wirings 30-4 electricallyconnected to the first output terminals of the circuits 17 in the secondcolumn 43-2, the wirings 30-3 electrically connected to the first outputterminals of the circuits 17 in the third column 43-3, and the wirings30-2 electrically connected to the second output terminals of thecircuits 17 in the first column 43-1 are electrically connected to theinput terminals of the circuits 17 in the second column 43-2 through theswitch circuits 31.

FIG. 10A is a circuit diagram of the switch circuit 31 that controlselectrical continuity between the wirings 30-2, 30-3, and 30-4 and theinput terminals of the circuits 17 in the second column 43-2 illustratedin FIG. 9. In FIG. 10A, a plurality of wirings 30-8 included in thewirings 30 are electrically connected to a plurality of input terminalsof the circuit 17 in the second column 43-2.

FIG. 10B illustrates a specific structural example of the switch circuit31 illustrated in FIG. 10A. The switch circuit 31 in FIG. 10A includesthree switch circuits 31 a as illustrated in FIG. 10B.

FIG. 10B illustrates the switch circuit 31 corresponding to threewirings 30-8 and thus shows the case where the switch circuit 31includes the three switch circuits 31 a. The number of the switchcircuits 31 a included in the switch circuit 31 can be determined inaccordance with the number of the input terminals of the circuit 17.

As a typical example, FIGS. 10A and 10B illustrate the switch circuit 31that controls electrical continuity between the wirings 30-2, 30-3, and30-4 and the wirings 30-8; other switch circuits 31 that controlelectrical continuity between a group of wirings 30 and another group ofwirings 30 in FIG. 9 have a structure similar to the above.

FIG. 10C illustrates a more specific structural example of the switchcircuit 31 in FIG. 10B. FIG. 10C more specifically shows a connectionrelation between the wirings 30-2, 30-3, and 30-4 and the switch circuit31. As illustrated in FIG. 10C, each of the switch circuits 31 acontrols electrical continuity between all the wirings 30-2, 30-3, and30-4 and one of the wirings 30-8.

The switch circuit 31 a illustrated in FIGS. 10B and 10C functions asthe memory circuit 19 illustrated in FIG. 1. That is, the switch circuit31 a has a function of storing the second data including circuitinformation as well as a function of controlling electrical continuitybetween the circuits 17 in accordance with the second data.

Next, a specific structural example of the switch circuit 31 a will bedescribed with reference to FIG. 11. The switch circuit 31 a illustratedin FIG. 11 includes a plurality of wirings BL shown as wirings BL-1 toBL-x (x is a natural number of 2 or more), a plurality of wirings OLshown as wirings OL-1 to OL-x, the wiring 30-8, a plurality of wiringsWL shown as wirings WL-1 to WL-y (y is a natural number of 2 or more),and a plurality of wirings CL shown as wirings CL-1 to CL-y.

When the switch circuit 31 a in FIG. 11 is used in FIG. 10C, the wirings30-2, 30-3, and 30-4 in FIG. 10C correspond to the wirings OL-1 to OL-xin FIG. 11.

The switch circuit 31 a in FIG. 11 also includes xxy circuits 45. Eachof the circuits 45 at least includes a transistor 47, a transistor 48, atransistor 49, and a capacitor 50. The xxy circuits 45 form y sets 46each of which is composed of x circuits 45 connected to the wiring WL-jand the wiring CL-j (j is a natural number of y or less). In FIG. 11,they sets 46 are shown as sets 46-1 to 46-y.

Specifically, in the circuit 45 in the j-th row and the i-th column (iis a natural number of x or less), a gate of the transistor 47 iselectrically connected to the wiring WL-j. One of a source and a drainof the transistor 47 is electrically connected to the wiring BL-i, andthe other thereof is electrically connected to a gate of the transistor48. One of a source and a drain of the transistor 48 is electricallyconnected to the wiring OL-i, and the other thereof is electricallyconnected to one of a source and a drain of the transistor 49. The otherof the source and the drain of the transistor 49 is electricallyconnected to the wiring 30-8. A gate of the transistor 49 iselectrically connected to the wiring CL-j. The capacitor 50 is connectedto the gate of the transistor 48.

The circuit 45 may further include another circuit element such as atransistor, a diode, a resistor, a capacitor, or an inductor as needed.

In the switch circuit 31 a in FIG. 11, when a potential of a signalincluding the second data is applied to the wiring BL while thetransistor 47 is on, the potential is supplied to the gate of thetransistor 48 through the transistor 47. Then, when the transistor 47 isturned off, the potential supplied to the gate of the transistor 48 ismaintained. The on/off state of the transistor 48 is selected dependingon the gate potential that reflects the second data.

Since the transistor 49 is electrically connected in series to thetransistor 48, the transistors 48 and 49 collectively have a function ofcontrolling electrical continuity between the wiring OL and the wiring30-8. Specifically, when the transistors 48 and 49 are on, electricalcontinuity is established between the wiring OL and the wiring 30-8.When at least one of the transistors 48 and 49 is off, the wiring OL andthe wiring 30-8 are electrically isolated from each other. That is,electrical continuity between the wirings OL and the wiring 30-8 isdetermined in accordance with the potential of a signal including thesecond data held in the circuits 45.

One of the circuits 17 illustrated in FIG. 9 is connected to the wiringOL, and one of the circuits 17 is connected to the wiring 30-8.Accordingly, electrical continuity between the circuits 17 is controlledin accordance with the second data written to the circuits 45 in theswitch circuit 31 a.

The switch circuit 31 a illustrated in FIG. 11 includes a switch 52 forcontrolling electrical continuity between the wiring 30-8 and a wiring51 supplied with a predetermined potential. In FIG. 11, one transistoris used as the switch 52. The switch 52 is turned on and off inaccordance with the signal INIT. Specifically, the potential of thewiring 51 is applied to the wiring 30-8 when the switch 52 is on,whereas the potential of the wiring 51 is not applied to the wiring 30-8when the switch 52 is off.

By turning on the switch 52, the potential of the wiring 30-8 can beinitialized to a predetermined level. Initialization of the potential ofthe wiring 30-8 prevents a large amount of current from flowing betweenthe wiring 30-8 and the wirings OL even when the potentials of thewiring 30-8 and the wirings OL are indefinite while the second data isretained. Thus, breakage of the integrated circuit 12 can be prevented.

In the period during which the second data is maintained, the potentialof the wiring 30-8 sometimes becomes intermediate between high-level andlow-level potentials. When the intermediate potential is applied to theinput terminal of the circuit 17, a shoot-through current is likely tobe generated in the circuit 17 connected to the wiring 30-8. However,since the potential of the wiring 30-8 can be initialized as describedabove, the input terminal can be prevented from having the intermediatepotential immediately after power is turned on; thus, generation of theshoot-through current can be prevented.

A latch may be electrically connected to the wiring 30-8. In FIG. 11, alatch 53 as well as the switch 52 for initialization is electricallyconnected to the wiring 30-8. The latch 53 has a function of keeping thepotential of the wiring 30-8 high or low. Electrically connecting thelatch 53 to the wiring 30-8 enables the potential of the wiring 30-8 tobe kept high or low, thereby preventing a shoot-through current frombeing generated in the circuit 17 whose input terminal is connected tothe wiring 30-8 by application of the intermediate potential to thewiring 30-8.

Specifically, the latch 53 in FIG. 11 includes a circuit 54 having afunction of inverting the polarity of a potential and a transistor 55.As the circuit 54, an inverter can be used, for example. An inputterminal of the circuit 54 is electrically connected to the wiring 30-8.An output terminal of the circuit 54 is electrically connected to a gateof the transistor 55. One of a source and a drain of the transistor 55is electrically connected to a wiring 56 supplied with a potentialhigher than a potential applied to the wiring 51. The other of thesource and the drain of the transistor 55 is electrically connected tothe wiring 30-8.

Note that the transistor 47 in the switch circuit 31 a of FIG. 11 ispreferably a transistor with ultralow off-state current because it has afunction of holding the gate potential of the transistor 48. Atransistor in which a channel formation region is formed in a film of asemiconductor with a wider band gap and lower intrinsic carrier densitythan silicon can have extremely low off-state current and thus ispreferably used as the transistor 47. Examples of such a semiconductorare an oxide semiconductor and gallium nitride each having a band gapmore than twice as wide as that of silicon. A transistor including theabove semiconductor can have much lower off-state current than atransistor including a normal semiconductor such as silicon orgermanium. Thus, the use of the transistor 47 having the above structurecan prevent leakage of electric charge held at the gate of thetransistor 48.

In the circuit 45 of the switch circuit 31 a in FIG. 11, the gate of thetransistor 48 is floating and highly insulated from other electrodes andwirings when the transistor 47 is off, so that a boosting effectdescribed below is obtained. Specifically, when the gate of thetransistor 48 is floating in the circuit 45, as the potential of thewiring OL changes from low level to high level, the gate potential ofthe transistor 48 is increased by a capacitance Cgs generated betweenthe source and the gate of the transistor 48 serving as a switch. Theamount of increase in the gate potential of the transistor 48 depends onthe logical level of a potential input to the gate of the transistor 48.Specifically, when the potential of the second data written to thecircuit 45 is a logical level “0”, the transistor 48 is in a weakinversion mode, so that the capacitance Cgs that contributes to anincrease in the gate potential of the transistor 48 includes acapacitance Cos that is independent of the gate potential of thetransistor 48. More specifically, the capacitance Cos includes anoverlap capacitance generated in a region where the gate electrode andthe source region overlap with each other, and a parasitic capacitancegenerated between the gate electrode and the source electrode, forexample. On the other hand, when the potential of the second datawritten to the circuit 45 is a logical level “1”, the transistor 48 isin a strong inversion mode, so that the capacitance Cgs includes part ofa capacitance Cox generated between a channel formation region and thegate electrode, in addition to the capacitance Cos. Thus, when thepotential of the second data is the logical level “1”, the capacitanceCgs is larger than that when the potential is the logical level “0”.Consequently, in the circuit 45, a boosting effect with which the gatepotential of the transistor 48 is further increased with a change in thepotential of the wiring OL is more enhanced when the potential of thesecond data is the logical level “1” than when the potential is thelogical level “0”. Thus, when the potential of the second data writtento the circuit 45 is the logical level “1”, the transistor 48 serving asa switch can be turned on and the switching speed of the circuit 45 canbe increased because the gate potential of the transistor 48 can beincreased by the boosting effect even if the gate potential of thetransistor 48 is lower than the potential of a signal including thesecond data input to the wiring BL by the threshold voltage of thetransistor 47. When the potential of the second data is the logicallevel “0”, the transistor 48 serving as a switch can remain off.

[Transistors]

Next, the description is made on a structural example of a transistor 80having a channel formation region in an oxide semiconductor film.

FIGS. 12A to 12C illustrate an example of the structure of thetransistor 80 that includes the channel formation region in the oxidesemiconductor film. FIG. 12A is a top view of the transistor 80. Notethat various insulating films are not illustrated in FIG. 12A in orderto clarify the layout of the transistor 80. FIG. 12B is across-sectional view along the dashed line A1-A2 in the top view in FIG.12A. FIG. 12C is a cross-sectional view along the dashed line A3-A4 inthe top view in FIG. 12A.

As illustrated in FIGS. 12A to 12C, the transistor 80 includes an oxidesemiconductor film 82 a and an oxide semiconductor film 82 b that arestacked in this order over an insulating film 81 formed over a substrate87; a conductive film 83 and a conductive film 84 that are electricallyconnected to the oxide semiconductor film 82 b and function as a sourceelectrode and a drain electrode; an oxide semiconductor film 82 c overthe oxide semiconductor film 82 b, the conductive film 83, and theconductive film 84; an insulating film 85 that functions as a gateinsulating film and is located over the oxide semiconductor film 82 c;and a conductive film 86 that functions as a gate electrode and overlapsthe oxide semiconductor films 82 a to 82 c with the insulating film 85placed therebetween. The substrate 87 may be a glass substrate, asemiconductor substrate, or an element substrate that is a glasssubstrate or a semiconductor substrate over which a semiconductorelement is formed.

FIGS. 13A to 13C illustrate another specific example of the structure ofthe transistor 80. FIG. 13A is a top view of the transistor 80. Notethat various insulating films are not illustrated in FIG. 13A in orderto clarify the layout of the transistor 80. FIG. 13B is across-sectional view along the dashed line A1-A2 in the top view in FIG.13A. FIG. 13C is a cross-sectional view along the dashed line A3-A4 inthe top view in FIG. 13A.

As illustrated in FIGS. 13A to 13C, the transistor 80 includes the oxidesemiconductor films 82 a to 82 c that are stacked in this order over theinsulating film 81; the conductive films 83 and 84 that are electricallyconnected to the oxide semiconductor film 82 c and function as a sourceelectrode and a drain electrode; the insulating film 85 that functionsas a gate insulating film and is located over the oxide semiconductorfilm 82 c, the conductive film 83, and the conductive film 84; and theconductive film 86 that functions as a gate electrode and overlaps theoxide semiconductor films 82 a to 82 c with the insulating film 85placed therebetween.

FIGS. 12A to 12C and FIGS. 13A to 13C illustrate the structure examplesof the transistor 80 in which the oxide semiconductor films 82 a to 82 care stacked. The oxide semiconductor film of the transistor 80 is notlimited to a stack including a plurality of oxide semiconductor filmsand may be a single oxide semiconductor film.

When the transistor 80 includes the semiconductor film including theoxide semiconductor films 82 a to 82 c stacked in this order, each ofthe oxide semiconductor films 82 a and 82 c is an oxide film thatcontains at least one of metal elements contained in the oxidesemiconductor film 82 b and whose lowest conduction band energy iscloser to the vacuum level than that of the oxide semiconductor film 82b by higher than or equal to 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV andlower than or equal to 2 eV, 1 eV, 0.5 eV, or 0.4 eV. The oxidesemiconductor film 82 b preferably contains at least indium becausecarrier mobility is increased.

When the transistor 80 includes the semiconductor film with the abovestructure, when an electric field is applied to the semiconductor filmby applying voltage to the gate electrode, a channel region is formed inthe oxide semiconductor film 82 b, which has the lowest conduction bandenergy among the oxide semiconductor films. That is, the oxidesemiconductor film 82 c provided between the oxide semiconductor film 82b and the insulating film 85 makes it possible to form the channelregion in the oxide semiconductor film 82 b, which is separated from theinsulating film 85.

Since the oxide semiconductor film 82 c contains at least one of themetal elements contained in the oxide semiconductor film 82 b, interfacescattering is less likely to occur at the interface between the oxidesemiconductor film 82 b and the oxide semiconductor film 82 c. Thus,carriers are not easily inhibited from moving at the interface,resulting in an increase in the field-effect mobility of the transistor80.

If an interface level is formed at the interface between the oxidesemiconductor film 82 a and the oxide semiconductor film 82 b, a channelregion is formed also in the vicinity of the interface; thus, thethreshold voltage of the transistor 80 varies. However, since the oxidesemiconductor film 82 a contains at least one of the metal elementscontained in the oxide semiconductor film 82 b, an interface level isless likely to be formed at the interface between the oxidesemiconductor film 82 a and the oxide semiconductor film 82 b.Accordingly, the above structure can reduce variations in the electricalcharacteristics of the transistors 80, such as the threshold voltage.

A plurality of oxide semiconductor films are preferably stacked so thatan interface level that inhibits carrier flow is not formed at theinterface between the oxide semiconductor films due to an impurityexisting between the oxide semiconductor films. This is because if animpurity exists between the stacked oxide semiconductor films, thecontinuity of the lowest conduction band energy between the oxidesemiconductor films is lost, and carriers are trapped or disappear byrecombination in the vicinity of the interface. By reducing an impurityexisting between the films, a continuous junction (here, particularly aU-shape well structure whose lowest conduction band energy is changedcontinuously between the films) is formed more easily than the case ofmerely stacking a plurality of oxide semiconductor films that contain atleast one common metal as a main component.

In order to form such a continuous energy band, the films need to bestacked successively without being exposed to the air by using amulti-chamber deposition system (sputtering system) provided with a loadlock chamber. Each chamber of the sputtering apparatus is preferablyevacuated to a high vacuum (to about 5×10⁻⁷ Pa to 1×10⁻⁴ Pa) by anadsorption vacuum pump such as a cryopump so that water and the likeacting as impurities for the oxide semiconductor are removed as much aspossible. Alternatively, a turbo molecular pump and a cold trap arepreferably used in combination to prevent backflow of gas into thechamber through an evacuation system.

To obtain a highly purified intrinsic oxide semiconductor, not only highvacuum evacuation of the chambers but also high purification of a gasused in the sputtering is important. When an oxygen gas or an argon gasused as the sputtering gas is highly purified to have a dew point of−40° C. or lower, preferably −80° C. or lower, more preferably −100° C.or lower, moisture and the like can be prevented from entering the oxidesemiconductor film as much as possible. Specifically, when the oxidesemiconductor film 82 b is an In-M-Zn oxide film (M is Ga, Y, Zr, La,Ce, or Nd) and a target having the atomic ratio of metal elements ofIn:M:Zn is used to form the oxide semiconductor film 82 b, x ₁/y₁ rangespreferably from ⅓ to 6, more preferably from 1 to 6 and z₁/y₁ rangespreferably from ⅓ and to 6, more preferably from 1 to 6. Note that z₁/y₁in the range of 1 to 6 facilitates formation of a c-axis alignedcrystalline oxide semiconductor (CAAC-OS) film as the oxidesemiconductor film 82 b. Typical examples of the atomic ratio of themetal elements of the target are In:M:Zn=1:1:1 and In:M:Zn=3:1:2.

Specifically, when the oxide semiconductor films 82 a and 82 c containan In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd) and the atomic ratio ofmetal elements of In to M and Zn in a target for forming the oxidesemiconductor films 82 a and 82 c is x₂:y₂:z, it is preferable thatx₂/y₂ be less than x₁/y₁ and that z₂/y₂ range from to ⅓ to 6, morepreferably from 1 and to 6. Note that z₂/y₂ in the range of 1 to 6facilitates formation of a CAAC-OS film as the oxide semiconductor films82 a and 82 c. Typical examples of the atomic ratio of the metalelements of the target are In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6,and In:M:Zn=1:3:8.

The oxide semiconductor films 82 a and 82 c each have a thickness of 3nm to 100 nm, preferably 3 nm to 50 nm. The oxide semiconductor film 82b has a thickness of 3 nm to 200 nm, preferably 3 nm to 100 nm, morepreferably 3 nm to 50 nm.

In the three-layer semiconductor film, each of the oxide semiconductorfilms 82 a to 82 c can be amorphous or crystalline. Note that the oxidesemiconductor film 82 b in which a channel region is formed ispreferably crystalline, in which case the transistor 80 can have stableelectrical characteristics.

Note that a channel formation region refers to a region of asemiconductor film of a transistor that overlaps with a gate electrodeand is located between a source electrode and a drain electrode. Achannel region refers to a region through which current mainly flows inthe channel formation region.

For example, when an In—Ga—Zn oxide film formed by sputtering is used aseach of the oxide semiconductor films 82 a and 82 c, the oxidesemiconductor films 82 a and 82 c can be deposited with the use of anIn—Ga—Zn oxide target containing In, Ga, and Zn at an atomic ratio of1:3:2. The deposition conditions can be as follows, for example: anargon gas (flow rate: 30 sccm) and an oxygen gas (flow rate: 15 sccm)are used as the deposition gas; the pressure is 0.4 Pa; the substratetemperature is 200° C.; and the DC power is 0.5 kW.

When the oxide semiconductor film 82 b is a CAAC-OS film, the oxidesemiconductor film 82 b is preferably deposited with the use of apolycrystalline In—Ga—Zn oxide target containing In, Ga, and Zn at anatomic ratio of 1:1:1. The deposition conditions can be as follows, forexample: an argon gas (flow rate: 30 sccm) and an oxygen gas (flow rate:15 sccm) are used as the deposition gas; the pressure is 0.4 Pa; thesubstrate temperature is 300° C.; and the DC power is 0.5 kW.

Although the oxide semiconductor films 82 a to 82 c can be formed bysputtering, they may be formed by another method, e.g., a thermal CVDmethod. Examples of a thermal CVD method include metal organic chemicalvapor deposition (MOCVD) and atomic layer deposition (ALD).

A highly purified oxide semiconductor (purified oxide semiconductor)obtained by reduction of impurities such as moisture or hydrogen servingas electron donors (donors) and reduction of oxygen vacancies has fewcarrier sources and thus can be an i-type (intrinsic) semiconductor or asubstantially i-type semiconductor. For this reason, a transistor havinga channel formation region in a highly purified oxide semiconductor filmexhibits extremely low off-state current and has high reliability. Atransistor including a channel formation region in the oxidesemiconductor film is likely to have positive threshold voltage (alsoreferred to as normally-off characteristics).

Specifically, various experiments can prove a low off-state current of atransistor having a channel formation region in a highly purified oxidesemiconductor film. For example, the off-state current of even anelement having a channel width of 1×10⁶ μm and a channel length of 10 μmcan be less than or equal to the measurement limit of a semiconductorparameter analyzer, that is, less than or equal to 1×10⁻¹³ A at avoltage between source and drain electrodes (drain voltage) of 1 V to 10V. In this case, it can be seen that off-state current standardized onthe channel width of the transistor is lower than or equal to 100 zA/μm.In addition, the off-state current is measured using a circuit in whicha capacitor and a transistor are connected to each other and electriccharge flowing into or from the capacitor is controlled by thetransistor. In the measurement, a highly purified oxide semiconductorfilm is used for a channel formation region of the transistor, and theoff-state current of the transistor is measured from a change in theamount of electric charge of the capacitor per unit time. As a result,it is found that when the voltage between the source and drainelectrodes of the transistor is 3 V, a lower off-state current ofseveral tens of yoctoamperes per micrometer (yA/μm) is obtained.Consequently, the transistor in which a highly purified oxidesemiconductor film is used for a channel formation region has much loweroff-state current than a transistor containing crystalline silicon.

When an oxide semiconductor film is used as the semiconductor film, theoxide semiconductor preferably contains at least indium (In) or zinc(Zn). Furthermore, as a stabilizer for reducing variations in electriccharacteristics of transistors using the oxide semiconductor, the oxidesemiconductor preferably contains gallium (Ga), tin (Sn), hafnium (Hf),aluminum (A1), and/or zirconium (Zr) in addition to indium (In) and/orzinc (Zn).

An In—Ga—Zn oxide and an In—Sn—Zn oxide among oxide semiconductors havethe following advantages over silicon carbide, gallium nitride, andgallium oxide: transistors with excellent electrical characteristics canbe formed by sputtering or a wet process and thus can be mass-producedeasily. Moreover, unlike in the case of using silicon carbide, galliumnitride, or gallium oxide, with the use of the In—Ga—Zn oxide,transistors with excellent electrical characteristics can be formed overa glass substrate, and a larger substrate can be used.

As another stabilizer, the oxide semiconductor may contain one or pluralkinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium(Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd),terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm),ytterbium (Yb), and lutetium (Lu).

As the oxide semiconductor, any of the following oxides can be used, forexample: indium oxide, gallium oxide, tin oxide, zinc oxide, In—Znoxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg oxide, In—Mg oxide,In—Ga oxide, In—Ga—Zn oxide (also referred to as IGZO), In—Al—Zn oxide,In—Sn—Zn oxide, Sn—Ga—Zn oxide, Al—Ga—Zn oxide, Sn—Al—Zn oxide, In—Hf—Znoxide, In—La—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In—Ce—Zn oxide,In—Sm—Zn oxide, In—Eu—Zn oxide, In—Gd—Zn oxide, In—Tb—Zn oxide, In—Dy—Znoxide, In—Ho—Zn oxide, In—Er—Zn oxide, In—Tm—Zn oxide, In—Yb—Zn oxide,In—Lu—Zn oxide, In—Sn—Ga—Zn oxide, In—Hf—Ga—Zn oxide, In—Al—Ga—Zn oxide,In—Sn—Al—Zn oxide, In—Sn—Hf—Zn oxide, and In—Hf—Al—Zn oxide.

For example, an In—Ga—Zn oxide refers to an oxide containing In, Ga, andZn, and there is no limitation on the ratio of In, Ga, and Zn.Furthermore, the In—Ga—Zn oxide may contain a metal element other thanIn, Ga, and Zn. The In—Ga—Zn oxide has sufficiently high resistance whenno electric field is applied thereto, so that off-state current can besufficiently reduced. Moreover, the In—Ga—Zn oxide has high mobility.

For example, high mobility can be obtained relatively easily with anIn—Sn—Zn oxide. Meanwhile, when an In—Ga—Zn oxide is used, the mobilitycan be increased by reduction in the defect density in a bulk.

In the transistor 80, a metal in the source and drain electrodes mightextract oxygen from the oxide semiconductor film depending on aconductive material used for the source and drain electrodes. In such acase, a region of the oxide semiconductor film in contact with thesource electrode or the drain electrode becomes an n-type region due tothe formation of an oxygen vacancy. The n-type region serves as a sourceregion or a drain region, resulting in a decrease in the contactresistance between the oxide semiconductor film and the source electrodeor the drain electrode. Thus, the formation of the n-type regionsincreases the mobility and the on-state current of the transistor 80,leading to high-speed operation of a semiconductor device using thetransistor 80.

Note that the extraction of oxygen by a metal in the source and drainelectrodes is probably caused when the source and drain electrodes areformed by sputtering or when heat treatment is performed after theformation of the source and drain electrodes. The n-type region is morelikely to be formed by forming the source and drain electrodes with theuse of a conductive material that is easily bonded to oxygen. Examplesof such a conductive material include Al, Cr, Cu, Ta, Ti, Mo, and W.

In the case where the semiconductor film including the stacked oxidesemiconductor films is used in the transistor 80, the n-type regionpreferably extends to the oxide semiconductor film 82 b serving as achannel region in order that the mobility and on-state current of thetransistor 80 can be increased and the semiconductor device can operateat higher speed.

The insulating film 81 preferably has a function of supplying oxygen tothe oxide semiconductor films 82 a to 82 c by heating. It is preferablethat the number of defects in the insulating film 81 be small, and thattypically the spin density of g=2.001 due to a dangling bond of siliconbe lower than or equal to 1×10¹⁸ spins/cm³. The spin density is measuredby ESR spectroscopy.

The insulating film 81 is preferably formed using an oxide to have afunction of supplying oxygen to the oxide semiconductor films 82 a to 82c by heating. Examples of the oxide include aluminum oxide, magnesiumoxide, silicon oxide, silicon oxynitride, silicon nitride oxide, galliumoxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, and tantalum oxide. The insulating film81 can be formed by plasma-enhanced CVD, sputtering, or the like.

Note that in this specification, oxynitride contains more oxygen thannitrogen, and nitride oxide contains more nitrogen than oxygen.

Note that in the transistor 80 illustrated in FIGS. 12A to 12C and FIGS.13A to 13C, the conductive film 86 overlaps end portions of the oxidesemiconductor film 82 b including a channel region that do not overlapthe conductive films 83 and 84, that is, end portions of the oxidesemiconductor film 82 b that are in a region different from regionswhere the conductive films 83 and 84 are located. If the end portions ofthe oxide semiconductor film 82 b are exposed to plasma by etching forforming the end portions, chlorine radical, fluorine radical, or thelike generated from an etching gas is easily bonded to a metal elementcontained in the oxide semiconductor. For this reason, in the endportions of the oxide semiconductor film, oxygen bonded to the metalelement is easily released, so that an oxygen vacancy is easily formedand the oxide semiconductor film easily has n-type conductivity.However, in the transistor 80 in FIGS. 12A to 12C and FIGS. 13A to 13C,since the end portions of the oxide semiconductor film 82 b that do notoverlap the conductive films 83 and 84 overlap with the conductive film86, an electric field applied to the end portions can be adjusted bycontrolling the potential of the conductive film 86. Consequently, theflow of current between the conductive films 83 and 84 through the endportions of the oxide semiconductor film 82 b can be controlled by thepotential supplied to the conductive film 86. This structure of thetransistor 80 is referred to as a surrounded channel (s-channel)structure.

Specifically, when a potential at which the transistor 80 is turned offis supplied to the conductive film 86, the s-channel structure canreduce the amount of off-state current that flows between the conductivefilms 83 and 84 through the end portions of the oxide semiconductor film82 b. For this reason, even when the distance between the conductivefilms 83 and 84 at the end portions of the oxide semiconductor film 82 bis reduced in the transistor 80 as a result of reducing the channellength to obtain high on-state current, the transistor 80 can exhibitlow off-state current. Thus, the transistor 80 with a short channellength can exhibit high on-state current and low off-state current.

Specifically, when a potential at which the transistor 80 is turned onis supplied to the conductive film 86, the s-channel structure canincrease the amount of current that flows between the conductive films83 and 84 through the end portions of the oxide semiconductor film 82 b.The current contributes to an increase in the field-effect mobility andon-state current of the transistor 80. When the end portions of theoxide semiconductor film 82 b overlap with the conductive film 86,carriers flow in a wide region of the oxide semiconductor film 82 bwithout being limited to a region in the vicinity of the interfacebetween the oxide semiconductor film 82 b and the insulating film 85,leading to an increase in the amount of carriers that move in thetransistor 80. As a result, the on-state current of the transistor 80 isincreased, and the field-effect mobility is increased to 10 cm²/Vs orhigher or to 20 cm²/V-s or higher, for example. Note that here,field-effect mobility is not an approximate value of the mobility as thephysical property of the oxide semiconductor film, but is an index ofcurrent drive capability in a saturation region of the transistor andapparent field-effect mobility.

A structure of the oxide semiconductor film is described below.

Note that in this specification, the term “parallel” indicates that anangle formed between two straight lines ranges from −10° to 10°, andaccordingly also includes the case where the angle ranges from −5° to5°. The term “substantially parallel” indicates that an angle formedbetween two straight lines ranges from −30° to 30°. The term“perpendicular” indicates that the angle formed between two straightlines ranges from 80° to 100°, and accordingly also includes the casewhere the angle ranges from 85° to 95°. The term “substantiallyperpendicular” indicates that an angle formed between two straight linesranges from 60° to 120°. In this specification, trigonal andrhombohedral crystal systems are included in a hexagonal crystal system.

An oxide semiconductor film is classified into a non-single-crystaloxide semiconductor film and a single crystal oxide semiconductor film.Alternatively, an oxide semiconductor is classified into a crystallineoxide semiconductor and an amorphous oxide semiconductor, for example.

Examples of a non-single-crystal oxide semiconductor include a c-axisaligned crystalline oxide semiconductor (CAAC-OS), a polycrystallineoxide semiconductor, a microcrystalline oxide semiconductor, and anamorphous oxide semiconductor. Examples of a crystalline oxidesemiconductor include a single crystal oxide semiconductor, a CAAC-OS, apolycrystalline oxide semiconductor, and a microcrystalline oxidesemiconductor.

First, a CAAC-OS film is described.

The CAAC-OS film is an oxide semiconductor film having a plurality ofc-axis aligned crystal parts.

With a transmission electron microscope (TEM), a combined analysis image(high-resolution TEM image) of a bright-field image and a diffractionpattern of the CAAC-OS film is observed, and a plurality of crystal partcan be clearly observed. However, in the high-resolution TEM image, aboundary between crystal parts, that is, a grain boundary is not clearlyobserved. Thus, in the CAAC-OS film, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

According to the high-resolution cross-sectional TEM image of theCAAC-OS film observed in a direction substantially parallel to a samplesurface, metal atoms are arranged in a layered manner in the crystalparts. Each metal atom layer reflects unevenness of a surface over whichthe CAAC-OS film is formed (hereinafter a surface over which the CAAC-OSfilm is formed is referred to as a formation surface) or a top surfaceof the CAAC-OS film, and is arranged parallel to the formation surfaceor the top surface of the CAAC-OS film.

In the high-resolution plan-view TEM image of the CAAC-OS film observedin a direction substantially perpendicular to the sample surface, metalatoms arranged in a triangular or hexagonal configuration are seen inthe crystal parts. However, there is no regularity of arrangement ofmetal atoms between different crystal parts.

A CAAC-OS film is subjected to structural analysis with an X-raydiffraction (XRD) apparatus. For example, when the CAAC-OS filmincluding an InGaZnO₄ crystal is analyzed by an out-of-plane method, apeak appears frequently at a diffraction angle (2θ) of around 31°. Thispeak is derived from the (009) plane of the InGaZnO₄ crystal, whichindicates that crystals in the CAAC-OS film have c-axis alignment, andthat the c-axes are aligned in a direction substantially perpendicularto the formation surface or the top surface of the CAAC-OS film.

When the CAAC-OS film with an InGaZnO₄ crystal is analyzed by anout-of-plane method, a peak may also be observed at 2θ of around 36° aswell as at 2θ of around 31°. The peak at 2θ of around 36° indicates thata crystal having no c-axis alignment is included in part of the CAAC-OSfilm. It is preferable that in the CAAC-OS film, a peak appear at 2θ ofaround 31° and a peak not appear at 2θ of around 36°.

The CAAC-OS film is an oxide semiconductor film having low impurityconcentration. The impurity is an element other than the main componentsof the oxide semiconductor film, such as hydrogen, carbon, silicon, or atransition metal element. In particular, an element that has higherbonding strength to oxygen than a metal element included in the oxidesemiconductor film, such as silicon, disturbs the atomic arrangement ofthe oxide semiconductor film by depriving the oxide semiconductor filmof oxygen and causes a decrease in crystallinity. A heavy metal such asiron or nickel, argon, carbon dioxide, or the like has a large atomicradius (molecular radius), and thus disturbs the atomic arrangement ofthe oxide semiconductor film and causes a decrease in crystallinity whenit is contained in the oxide semiconductor film. Note that the impuritycontained in the oxide semiconductor film might serve as a carrier trapor a carrier generation source.

The CAAC-OS film is an oxide semiconductor film having a low density ofdefect states. In some cases, oxygen vacancies in the oxidesemiconductor film serve as carrier traps or serve as carrier generationsources when hydrogen is captured therein.

The state in which the impurity concentration is low and the density ofdefect states is low (the number of oxygen vacancies is small) isreferred to as a “highly purified intrinsic” or “substantially highlypurified intrinsic” state. A highly purified intrinsic or substantiallyhighly purified intrinsic oxide semiconductor film has few carriergeneration sources, and thus can have a low carrier density. Thus, atransistor including the oxide semiconductor film rarely has negativethreshold voltage (rarely has normally-on characteristics). The highlypurified intrinsic or substantially highly purified intrinsic oxidesemiconductor film has a low density of defect states and thus has fewcarrier traps. Consequently, the transistor including the oxidesemiconductor film has little variation in electrical characteristicsand high reliability. Electric charge trapped by the carrier traps inthe oxide semiconductor film takes a long time to be released and mightbehave like fixed electric charge. Thus, the transistor including theoxide semiconductor film having high impurity concentration and a highdensity of defect states has unstable electrical characteristics in somecases.

With the use of the CAAC-OS film in a transistor, variation in theelectrical characteristics of the transistor due to irradiation withvisible light or ultraviolet light is small.

Next, a microcrystalline oxide semiconductor film is described.

In a high-resolution TEM image of a microcrystalline oxide semiconductorfilm, there are a region where a crystal part is observed and a regionwhere a crystal part is not clearly observed. In most cases, a crystalpart in the microcrystalline oxide semiconductor ranges from 1 nm to 100nm, or from 1 nm to 10 nm. A microcrystal with a size in the range of 1nm to 10 nm or of 1 nm to 3 nm is specifically referred to asnanocrystal (nc). An oxide semiconductor film including nanocrystal isreferred to as a nanocrystalline oxide semiconductor (nc-OS) film. In ahigh-resolution TEM image of the nc-OS film, a grain boundary cannot befound clearly in some cases.

In the nc-OS film, a microscopic region (e.g., a region with a sizeranging from 1 nm to 10 nm, in particular, from 1 nm to 3 nm) has aperiodic atomic order. There is no regularity of crystal orientationbetween different crystal parts in the nc-OS film. Thus, the orientationof the whole film is not observed. Consequently, in some cases, thenc-OS film cannot be distinguished from an amorphous oxide semiconductorfilm depending on an analysis method. For example, when the nc-OS filmis subjected to structural analysis by an out-of-plane method with anXRD apparatus using an X-ray having a diameter larger than that of acrystal part, a peak showing a crystal plane does not appear. Adiffraction pattern like a halo pattern appears in a selected-areaelectron diffraction pattern of the nc-OS film obtained by using anelectron beam having a probe diameter larger than the diameter of acrystal part (e.g., having a probe diameter of 50 nm or larger).Meanwhile, spots are shown in a nanobeam electron diffraction pattern ofthe nc-OS film obtained by using an electron beam having a probediameter close to or smaller than the diameter of a crystal part.Furthermore, in a nanobeam electron diffraction pattern of the nc-OSfilm, regions with high luminance in a circular (ring) pattern aresometimes shown. Also in a nanobeam electron diffraction pattern of thenc-OS film, a plurality of spots are sometimes shown in a ring-likeregion.

The nc-OS film is an oxide semiconductor film that has higher regularitythan an amorphous oxide semiconductor film, and therefore has a lowerdensity of defect states than an amorphous oxide semiconductor film.However, there is no regularity of crystal orientation between differentcrystal parts in the nc-OS film; hence, the nc-OS film has a higherdensity of defect states than the CAAC-OS film.

Next, an amorphous oxide semiconductor film is described.

The amorphous oxide semiconductor film has disordered atomic arrangementand no crystal part. An example of the amorphous oxide semiconductorfilm is an oxide semiconductor film with a non-crystalline state likequartz glass.

In a high-resolution TEM image of the amorphous oxide semiconductorfilm, crystal parts cannot be found.

When the amorphous oxide semiconductor film is subjected to structuralanalysis by an out-of-plane method with an XRD apparatus, a peak showinga crystal plane does not appear. A halo pattern is shown in an electrondiffraction pattern of the amorphous oxide semiconductor film.Furthermore, a halo pattern is shown but a spot is not shown in ananobeam electron diffraction pattern of the amorphous oxidesemiconductor film.

Note that an oxide semiconductor film may have a structure with physicalproperties between the nc-OS film and the amorphous oxide semiconductorfilm. The oxide semiconductor film having such a structure isspecifically referred to as an amorphous-like oxide semiconductor(a-like OS) film.

In a high-resolution TEM image of the a-like OS film, a void may beseen. Furthermore, in the high-resolution TEM image, there are a regionwhere a crystal part is clearly observed and a region where a crystalpart is not observed. In the a-like OS film, crystallization occurs by aslight amount of electron beam used for TEM observation and growth ofthe crystal part is found in some cases. In contrast, crystallizationdue to a slight amount of electron beam used for TEM observation ishardly observed in the nc-OS film having good quality.

Note that the crystal part size in the a-like OS film and the nc-OS filmcan be measured using high-resolution TEM images. For example, anInGaZnO₄ crystal has a layered structure in which two Ga—Zn—O layers areincluded between In—O layers. A unit cell of the InGaZnO₄ crystal has astructure in which nine layers of three In—O layers and six Ga—Zn—Olayers are layered in the c-axis direction. Thus, the spacing betweenthese adjacent layers is substantially equivalent to the lattice spacing(also referred to as d value) on the (009) plane, and is 0.29 nmaccording to crystal structure analysis. Consequently, focusing on thelattice fringes in the high-resolution TEM image, lattice fringes with aspacing ranging from 0.28 nm to 0.30 nm each correspond to the a-b planeof the InGaZnO₄ crystal.

The density of an oxide semiconductor film might vary depending on itsstructure. For example, when the composition of an oxide semiconductorfilm becomes clear, the structure of the oxide semiconductor film can beestimated from a comparison between the density of the oxidesemiconductor film and the density of a single crystal oxidesemiconductor film having the same composition as the oxidesemiconductor film. For instance, the density of an a-like OS film is78.6% or higher and lower than 92.3% of the density of the singlecrystal oxide semiconductor film. In addition, for example, the densityof an nc-OS film or a CAAC-OS film is 92.3% or higher and lower than100% of the density of the single crystal oxide semiconductor film. Notethat it is difficult to deposit an oxide semiconductor film whosedensity is lower than 78% of the density of the single crystal oxidesemiconductor film.

A specific example of the above is described. For example, in an oxidesemiconductor film with an atomic ratio of In:Ga:Zn=1:1:1, the densityof single crystal InGaZnO₄ with a rhombohedral crystal structure is6.357 g/cm³. Thus, for example, the density of an a-like OS film with anatomic ratio of In:Ga:Zn=1:1:1 is higher than or equal to 5.0 g/cm³ andlower than 5.9 g/cm³. Moreover, for example, the density of an nc-OSfilm or a CAAC-OS film with an atomic ratio of In:Ga:Zn=1:1:1 is higherthan or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that single crystals with the same composition do not exist in somecases. In such a case, by combining single crystals with differentcompositions at a given proportion, it is possible to calculate adensity that corresponds to the density of a single crystal with adesired composition. The density of the single crystal with a desiredcomposition may be calculated using weighted average with respect to thecombination ratio of the single crystals with different compositions.Note that it is preferable to combine as few kinds of single crystals aspossible for density calculation.

Note that an oxide semiconductor film may be a stacked film includingtwo or more films of an amorphous oxide semiconductor film, an a-like OSfilm, a microcrystalline oxide semiconductor film, and a CAAC-OS film,for example.

For the deposition of the CAAC-OS film, the following conditions arepreferably used. Decay of the crystal state due to impurities can beprevented by reducing the amount of impurities entering the CAAC-OS filmduring the deposition, for example, by reducing the concentration ofimpurities (e.g., hydrogen, water, carbon dioxide, and nitrogen) thatexist in a treatment chamber or by reducing the concentration ofimpurities in a deposition gas. Specifically, a deposition gas with adew point of −80° C. or lower, preferably −100° C. or lower is used.

By increasing the substrate heating temperature during the deposition,migration of a sputtered particle occurs after the sputtered particlereaches a substrate. Specifically, the substrate heating temperatureduring the deposition ranges from 100° C. to 740° C., preferably from200° C. to 500° C. When the substrate heating temperature during thedeposition is increased and flat-plate-like or pellet-like sputteredparticles reach the substrate, migration occurs on the substrate, and aflat plane of each sputtered particle is attached to the substrate.

It is preferable that the proportion of oxygen in the deposition gas beincreased and the power be optimized in order to reduce plasma damage inthe deposition. The proportion of oxygen in the deposition gas is 30 vol% or higher, preferably 100 vol %.

As an example of the target, an In—Ga—Zn oxide target is describedbelow.

A polycrystalline In—Ga—Zn oxide target is made by mixing InO_(X)powder, GaO_(Y) powder, and ZnO_(Z) powder in a predetermined molarratio, applying pressure, and performing heat treatment at a temperatureof 1000° C. to 1500° C. Note that X, Y, and Z are each a given positivenumber. Here, the predetermined molar ratio of InO_(X) powder to GaO_(Y)powder and ZnO_(Z) powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1,4:2:3, or 3:1:2. The kinds of powder and the molar ratio for mixingpowder can be determined as appropriate depending on the desired target.

Alkali metal is not a constituent element of an oxide semiconductor andthus is an impurity. Likewise, alkaline earth metal is an impurity whenthe alkaline earth metal is not a constituent element of the oxidesemiconductor. When an insulating film in contact with an oxidesemiconductor film is an oxide, Na, among the alkali metals, diffusesinto the insulating film and becomes Na⁺. Furthermore, in the oxidesemiconductor film, Na cuts or enters a bond between metal and oxygenthat are constituent elements of the oxide semiconductor. As a result,the electrical characteristics of the transistor deteriorate, forexample, the transistor is placed in a normally-on state because of anegative shift of the threshold voltage or the mobility is decreased. Inaddition, the characteristics of transistors vary. Specifically, the Naconcentration measured by secondary ion mass spectrometry is preferably5×10¹⁶/cm³ or lower, more preferably 1×10¹⁶/cm³ or lower, still morepreferably 1×10¹⁵/cm³ or lower. Similarly, the measured Li concentrationis preferably 5×10¹⁵/cm³ or lower, more preferably 1×10¹⁵/cm³ or lower.Similarly, the measured K concentration is preferably 5×10¹⁵/cm³ orlower, more preferably 1×10¹⁵/cm³ or lower.

In the case where metal oxide containing indium is used, silicon orcarbon having higher bond energy with oxygen than indium might cut thebond between indium and oxygen, and an oxygen vacancy may be formed.Accordingly, like alkali metal or alkaline earth metal, silicon orcarbon contained in the oxide semiconductor film is likely to causedeterioration of the electric characteristics of the transistor. Thus,the concentrations of silicon and carbon in the oxide semiconductor filmare preferably low. Specifically, the C concentration or the Siconcentration measured by secondary ion mass spectrometry is preferably1×10¹⁸/cm³ or lower. In this case, the deterioration of the electriccharacteristics of the transistor can be prevented, so that thereliability of a semiconductor device can be improved.

Example of Cross-Sectional Structure of Semiconductor Device

FIG. 14 illustrates an example of a cross-sectional structure of thetransistor 47 and the transistor 48 included in the switch circuit 31 aillustrated in FIG. 11. A region along the dashed line A1-A2 showsstructures of the transistors 47 and 48 in the channel length direction,and a region along the dashed line A3-A4 shows structures of thetransistors 47 and 48 in the channel width direction. Note that in oneembodiment of the present invention, the channel length direction of thetransistor 47 is not necessarily the same as the channel lengthdirection of the transistor 48.

The channel length direction denotes a direction in which carriers moveat the shortest distance between a pair of impurity regions serving as asource region and a drain region. The channel width direction denotes adirection perpendicular to the channel length direction in a planeparallel to a substrate.

In FIG. 14, the transistor 47 including a channel formation region in anoxide semiconductor film is formed over the transistor 48 including achannel formation region in a single crystal silicon substrate.

The transistor 48 may include the channel formation region in asemiconductor film or a semiconductor substrate of silicon, germanium,or the like in an amorphous, microcrystalline, polycrystalline, orsingle crystal state. Alternatively, the transistor 48 may include thechannel formation region in an oxide semiconductor film or an oxidesemiconductor substrate. In the case where channel formation regions ofall the transistors are included in an oxide semiconductor film or anoxide semiconductor substrate, the transistor 47 is not necessarilystacked over the transistor 48, and the transistors 47 and 48 may beformed in the same layer.

When the transistor 48 is formed using a thin silicon film, any of thefollowing can be used, for example: amorphous silicon formed bysputtering or vapor phase growth such as plasma-enhanced CVD;polycrystalline silicon obtained by crystallization of amorphous siliconby laser annealing or the like; and single crystal silicon obtained byseparation of a surface portion of a single crystal silicon wafer byimplantation of hydrogen ions or the like into the silicon wafer.

A substrate 400 where the transistor 48 is Ruined can be, for example, asilicon substrate, a germanium substrate, or a silicon germaniumsubstrate. In FIG. 14, a single crystal silicon substrate is used as thesubstrate 400.

The transistor 48 is electrically isolated by an element isolationmethod. An example of the element isolation method is a trench isolationmethod (shallow trench isolation: STI). FIG. 14 illustrates an examplewhere the trench isolation method is used to electrically isolate thetransistor 48. Specifically, in FIG. 14, the transistor 48 iselectrically isolated by using an element isolation insulating region401 formed in such a manner that an insulator containing silicon oxideor the like is buried in a trench formed in the substrate 400 by etchingor the like and then the insulator is removed partly by etching or thelike.

In a projection of the substrate 400 that exists in a region other thanthe trench, an impurity region 402 and an impurity region 403 of thetransistor 48 and a channel formation region 404 placed between theimpurity regions 402 and 403 are provided. The transistor 48 alsoincludes an insulating film 405 covering the channel formation region404 and a gate electrode 406 that overlaps the channel formation region404 with the insulating film 405 placed therebetween.

In the transistor 48, a side portion and an upper portion of theprojection in the channel formation region 404 overlaps with the gateelectrode 406 with the insulating film 405 positioned therebetween, sothat carriers flow in a wide area (including a side portion and an upperportion of the channel formation region 404). Thus, an area over thesubstrate occupied by the transistor 48 is reduced, and the number oftransferred carriers in the transistor 48 is increased. As a result, thefield-effect mobility and on-state current of transistor 48 areincreased. Suppose the length of the projection of the channel formationregion 404 in the channel width direction (i.e., channel width) is W andthe thickness of the projection of the channel formation region 404 isT. When the aspect ratio that corresponds to the ratio of the thicknessT to the channel width W is high, a region where carrier flows becomeswider. Thus, the on-state current and field-effect mobility of thetransistor 48 can be further increased.

Note that when the transistor 48 is formed using a bulk semiconductorsubstrate, the aspect ratio is preferably 0.5 or more, furtherpreferably 1 or more.

An insulating film 411 is provided over the transistor 48. Openings areformed in the insulating film 411. A conductive film 412, a conductivefilm 413, and a conductive film 414 that are electrically connected tothe impurity region 402, the impurity region 403, and the gate electrode406, respectively, are formed in the openings.

The conductive film 412 is electrically connected to a conductive film416 over the insulating film 411. The conductive film 413 iselectrically connected to a conductive film 417 over the insulating film411. The conductive film 414 is electrically connected to a conductivefilm 418 over the insulating film 411.

An insulating film 420 is provided over the conductive films 416 to 418.An insulating film 421 having an effect of blocking diffusion of oxygen,hydrogen, and water is provided over the insulating film 420. As theinsulating film 421 has higher density and becomes denser or has a fewerdangling bonds and becomes more chemically stable, the insulating film421 has a higher blocking effect. The insulating film 421 having aneffect of blocking diffusion of oxygen, hydrogen, and water can beformed using, for example, aluminum oxide, aluminum oxynitride, galliumoxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafniumoxide, or hafnium oxynitride. The insulating film 421 having an effectof blocking diffusion of hydrogen and water can be formed using siliconnitride or silicon nitride oxide, for example.

An insulating film 422 is provided over the insulating film 421. Thetransistor 47 is provided over the insulating film 422.

The transistor 47 includes, over the insulating film 422, asemiconductor film 430 containing an oxide semiconductor, conductivefilms 432 and 433 that are electrically connected to the semiconductorfilm 430 and functions as source and drain electrodes, a gate insulatingfilm 431 covering the semiconductor film 430, and a gate electrode 434that overlaps the semiconductor film 430 with the gate insulating film431 positioned therebetween. An opening is formed in the insulatingfilms 420 to 422. The conductive film 433 is connected to the conductivefilm 418 in the opening.

Note that in FIG. 14, the transistor 47 includes the gate electrode 434on at least one side of the semiconductor film 430; alternatively, thetransistor 47 may also include a gate electrode that overlaps thesemiconductor film 430 with the insulating film 422 placed therebetween.

When the transistor 47 includes a pair of gate electrodes, one of thegate electrodes may be supplied with a signal for controlling the on/offstate, and the other of the gate electrodes may be supplied with apotential from another element. In this case, potentials with the samelevel may be supplied to the pair of gate electrodes, or a fixedpotential such as a ground potential may be supplied only to the otherof the gate electrodes. By controlling the level of a potential suppliedto the other of the gate electrodes, the threshold voltage of thetransistor can be controlled.

In FIG. 14, the transistor 47 has a single-gate structure where onechannel formation region corresponding to one gate electrode 434 isprovided. Alternatively, the transistor 47 may have a multi-gatestructure where a plurality of gate electrodes electrically connected toeach other are provided so that a plurality of channel formation regionsare included in one active film.

FIG. 14 illustrates the example in which the semiconductor film 430 inthe transistor 47 includes the oxide semiconductor films 430 a to 430 cthat are stacked in this order over the insulating film 422. However, inone embodiment of the present invention, the semiconductor film 430 ofthe transistor 47 may be a single metal oxide film.

Examples of Electronic Device

The semiconductor device of one embodiment of the present invention canbe used for display devices, personal computers, and image reproducingdevices provided with recording media (typically, devices that reproducethe content of recording media such as digital versatile discs (DVD) andhave displays for displaying the reproduced images). Other examples ofelectronic devices that can be equipped with the semiconductor device ofone embodiment of the present invention are mobile phones, game machinesincluding portable game consoles, portable information appliances,e-book readers, cameras such as video cameras and digital still cameras,goggle-type displays (head mounted displays), navigation systems, audioreproducing devices (e.g., car audio systems and digital audio players),copiers, facsimiles, printers, multifunction printers, automated tellermachines (ATM), vending machines, and medical equipment. FIGS. 15A to15F illustrate specific examples of such electronic devices.

FIG. 15A illustrates a portable game console including a housing 5001, ahousing 5002, a display portion 5003, a display portion 5004, amicrophone 5005, speakers 5006, a control key 5007, a stylus 5008, andthe like. The semiconductor device of one embodiment of the presentinvention can be used for a variety of integrated circuits included inthe portable game console. Although the portable game consoleillustrated in FIG. 15A has the two display portions 5003 and 5004, thenumber of display portions included in a portable game console is notlimited to two.

FIG. 15B illustrates a portable information appliance including a firsthousing 5601, a second housing 5602, a first display portion 5603, asecond display portion 5604, a joint 5605, an operation key 5606, andthe like. The semiconductor device of one embodiment of the presentinvention can be used for a variety of integrated circuits included inthe portable information appliance. The first display portion 5603 isprovided in the first housing 5601, and the second display portion 5604is provided in the second housing 5602. The first housing 5601 and thesecond housing 5602 are connected to each other with the joint 5605, andthe angle between the first housing 5601 and the second housing 5602 canbe changed with the joint 5605. Images displayed on the first displayportion 5603 may be switched in accordance with the angle at the joint5605 between the first housing 5601 and the second housing 5602. Adisplay device with a position input function may be used as at leastone of the first display portion 5603 and the second display portion5604. Note that the position input function can be added by providing atouch panel in a display device or by providing a photoelectricconversion element called a photosensor in a pixel area of a displaydevice.

FIG. 15C illustrates a laptop including a housing 5401, a displayportion 5402, a keyboard 5403, a pointing device 5404, and the like. Thesemiconductor device of one embodiment of the present invention can beused for a variety of integrated circuits included in the laptop.

FIG. 15D illustrates an electric refrigerator-freezer including ahousing 5301, a refrigerator door 5302, a freezer door 5303, and thelike. The semiconductor device of one embodiment of the presentinvention can be used for a variety of integrated circuits included inthe electric refrigerator-freezer.

FIG. 15E illustrates a video camera including a first housing 5801, asecond housing 5802, a display portion 5803, an operation key 5804, alens 5805, a joint 5806, and the like. The semiconductor device of oneembodiment of the present invention can be used for a variety ofintegrated circuits included in the video camera. The operation key 5804and the lens 5805 are provided in the first housing 5801. The displayportion 5803 is provided in the second housing 5802. The first housing5801 and the second housing 5802 are connected to each other with thejoint 5806, and the angle between the first housing 5801 and the secondhousing 5802 can be changed with the joint 5806. Images displayed on thedisplay portion 5803 may be switched in accordance with the angle at thejoint 5806 between the first housing 5801 and the second housing 5802.

FIG. 15F illustrates a passenger car including a car body 5101, wheels5102, a dashboard 5103, lights 5104, and the like. The semiconductordevice of one embodiment of the present invention can be used for avariety of integrated circuits included in the passenger car.

This application is based on Japanese Patent Application serial no.2013-241608 filed with Japan Patent Office on Nov. 22, 2013, the entirecontents of which are hereby incorporated by reference.

What is claimed is:
 1. (canceled)
 2. An electronic device comprising: afirst circuit comprising a first memory; and a second circuit comprisinga second memory and a logic array, wherein the first memory isconfigured to store first data corresponding to a history of a firstbranch instruction of the first circuit, wherein the second memory isconfigured to store second data for controlling electrical continuitybetween circuits in the logic array and an output signal with respect toan input signal of the circuits in the logic array to generate a signalfor testing an operating state of the first circuit in a test for theoperating state of the first circuit, and third data corresponding to ahistory of a second branch instruction of the first circuit in normaloperation after the test, and wherein the electronic device is at leastone of a display device, a personal computer, an image reproducingdevice, a mobile phone, game machine, a portable information appliance,an e-book reader, a video camera, a digital still camera, a goggle-typedisplay, a head mounted display, an navigation system, an audioreproducing device, a copier, a facsimile, a printer, a multifunctionprinter, an automated teller machines, a vending machines, and a medicalequipment.
 3. The electronic device according to claim 2, wherein thesecond memory comprises a first transistor and a second transistor, andwherein a first terminal of the first transistor is electricallyconnected to a gate of the second transistor.
 4. The electronic deviceaccording to claim 3, wherein an on/off state of the second transistoris selected according to the second data input through the firsttransistor.
 5. The electronic device according to claim 3, wherein thefirst transistor comprises a channel formation region comprising anoxide semiconductor.
 6. The electronic device according to claim 5,wherein the oxide semiconductor comprises at least one of In, Ga, andZn.
 7. An electronic device comprising: a first circuit comprising afirst memory and a comparator circuit; and a second circuit comprising asecond memory and a logic array, wherein the first memory is configuredto store first data corresponding to a history of a first branchinstruction of the first circuit and a first address of the first branchinstruction, wherein the comparator circuit is configured to compare anaddress of an instruction and the first address, wherein the secondmemory is configured to store second data for controlling electricalcontinuity between circuits in the logic array and an output signal withrespect to an input signal of the circuits in the logic array togenerate a signal for testing an operating state of the first circuit ina test for the operating state of the first circuit, and third datacorresponding to a history of a second branch instruction of the firstcircuit and a second address of the second branch instruction in normaloperation after the test, and wherein the electronic device is at leastone of a display device, a personal computer, an image reproducingdevice, a mobile phone, game machine, a portable information appliance,an e-book reader, a video camera, a digital still camera, a goggle-typedisplay, a head mounted display, an navigation system, an audioreproducing device, a copier, a facsimile, a printer, a multifunctionprinter, an automated teller machines, a vending machines, and a medicalequipment.
 8. The electronic device according to claim 7, wherein thesecond memory comprises a first transistor and a second transistor, andwherein a first terminal of the first transistor is electricallyconnected to a gate of the second transistor.
 9. The electronic deviceaccording to claim 8, wherein an on/off state of the second transistoris selected according to the second data input through the firsttransistor.
 10. The electronic device according to claim 8, wherein thefirst transistor comprises a channel formation region comprising anoxide semiconductor.
 11. The electronic device according to claim 10,wherein the oxide semiconductor comprises at least one of In, Ga, andZn.
 12. The electronic device according to claim 7, wherein the firstcircuit comprises a selector circuit configured to select the firstaddress in accordance with a comparison result of the comparatorcircuit.
 13. The electronic device according to claim 12, wherein thesecond memory comprises a first transistor and a second transistor, andwherein a first terminal of the first transistor is electricallyconnected to a gate of the second transistor.
 14. The electronic deviceaccording to claim 13, wherein an on/off state of the second transistoris selected according to the second data input through the firsttransistor.
 15. The electronic device according to claim 13, wherein thefirst transistor comprises a channel formation region comprising anoxide semiconductor.
 16. The electronic device according to claim 15,wherein the oxide semiconductor comprises at least one of In, Ga, andZn.
 17. An electronic device comprising: a processor comprising a branchprediction circuit; and a programmable logic device, wherein theprogrammable logic device is a first configuration of a test circuit fortesting an operating state of the processor in a test for the operatingstate of the processor and a second configuration of an additional partof the branch prediction circuit in a normal operation after the test,and wherein the electronic device is at least one of a display device, apersonal computer, an image reproducing device, a mobile phone, gamemachine, a portable information appliance, an e-book reader, a videocamera, a digital still camera, a goggle-type display, a head mounteddisplay, an navigation system, an audio reproducing device, a copier, afacsimile, a printer, a multifunction printer, an automated tellermachines, a vending machines, and a medical equipment.
 18. Theelectronic device according to claim 17, wherein the programmable logicdevice comprises a memory comprising a first transistor and a secondtransistor, and wherein a first terminal of the first transistor iselectrically connected to a gate of the second transistor.
 19. Theelectronic device according to claim 18, wherein the first transistorcomprises a channel formation region comprising an oxide semiconductor.20. The electronic device according to claim 19, wherein the oxidesemiconductor comprises at least one of In, Ga, and Zn.